The disclosed embodiments of the present invention relate to frequency modulation using a digitally-controlled oscillator (DCO), and more particularly, to a frequency modulator having a DCO arranged for receiving a modulation tuning word and a phase-locked loop (PLL) tuning word and/or arranged for receiving a fractional tuning word obtained through asynchronous sampling and an integer tuning word.
All-digital phase-locked loop (ADPLL) based transmitters are becoming increasingly used instead of conventional analog in-phase/quadrature (I/Q) based transmitters. Specifically, an ADPLL can be used to provide not only a single-frequency sinusoidal radio-frequency (RF) carrier but could be turned into a wideband frequency modulator as part, for example, of a polar transmitter. The additional effort to support such a wideband frequency modulation (FM) is quite straightforward and is typically done using a digital two-point modulation scheme. The digital two-point modulation scheme may merge the higher-rate FM sample stream and a lower-rate PLL sample stream, such that one data stream of a higher sampling rate is presented to a DCO. In one conventional design, the merging of two data streams in the digital domain may require an interpolator or a resampler, which increases complexity and power consumption. In addition, the wide modulation bandwidths required by most advanced wireless standards are significantly pushing the limits of the digital polar transmitter. Hence, there is a need to extend the FM bandwidth without the necessity of an excessive complexity and/or power consumption.
If the DCO requires a fine frequency resolution, a digital tuning word generated from a digital FM processing circuit to the DCO is divided into an integer part and a fractional part. A sigma-delta modulation (SDM)-based dithering is employed to process the fractional part according to an oversampling clock. In general, each of the digital FM processing circuit and the SDM circuit operates according to a down-divided clock signal derived from frequency division of a DCO clock. The clock rate of the clock signal used by the SDM circuit is higher than the clock rate of the clock signal employed by the digital FM processing circuit. Unfortunately, a deep clock tree (typically consisting of a tree-like structure of inverters and buffers, some of them having clock gating capability) is required by the digital FM processing circuit due to substantially larger circuitry, and balancing the clock tree delays is difficult. This would result in higher digital circuit cost. Besides, the required synchronicity between the integer part and the fractional part in the digital domain might put unnecessary burden on design time and power consumption.